The present invention relates to the field of data transfer, and more particularly, to a method for buffering data between two asynchronous data buses having different widths.
There are many applications where it is necessary to transfer data from one asynchronous device to another, where each device has a different bus width. For example, a typical application where this situation arises is the case where it is necessary for a computer to transfer 16-bit words to a peripheral device that only accepts 12-bit words. The 16-bit word output of the computer must be repacked into 12-bit words. This requires different data word transfer rates for each data bus so that the peripheral device will be able to accept the data.
The conventional method of repacking data uses a CPU and software. The CPU must have sufficient speed to keep up with the input source data rate, and a data path that does not interfere with other system tasks being performed. In the case of some VME bus systems, the data paths are already fully utilized, and a medium-priced CPU is not fast enough to repack data at input source data rates approaching 2 Mb/sec.
Thus, there is a need for a method for repacking data that uses hardware logic, rather than software running on a CPU.